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          "id": "3",
          "name": "void cudnn::nhwcToNchwKernel<float, float, float, 1, 0, 0>(cudnn::nhwc2nchw_params_t<T3>, const T1 *, T2 *)",
          "category": "layout_conversion",
          "duration_us": 6.496
        },
        {
          "id": "4",
          "name": "void at::elementwise_kernel<128, 2, void at::gpu_kernel_impl_nocast<at::CUDAFunctor_add<float>>(at::TensorIteratorBase &, const T1 &)::[lambda(int) (instance 1)]>(int, T3)",
          "category": "elementwise_add",
          "duration_us": 3.584
        }
      ]
    }
  ],
  "audit_sha256": "1cd20f22b13dc6e63fd8ed5890420ce4a45db249f756f777f977848cf494bed8",
  "scope": "Disjoint categories inferred from explicit native kernel names, all9 newly profiled conv signatures. Fractions of summed isolated NCU kernel durations, not integrated wall clock, recoverable speedup, hardware overlap or causal optimization proof. Layout changes require controlled numerical and full-cost comparison; previous layout-negative result is another input."
}