{
  "status": "passed",
  "generated_at": "2026-09-10T03:58:12.877030+00:00",
  "allocated": "6",
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        "dram__bytes_read.sum": {
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          "unit": "Mbyte"
        },
        "dram__bytes_write.sum": {
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          "unit": "Mbyte"
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        "lts__t_sectors.sum": {
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      "dram_to_algorithm_ratio": 0.8091379801432291,
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        "dram__bytes_read.sum": {
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        "dram__bytes_write.sum": {
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        "lts__t_sectors.sum": {
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          "unit": "sector"
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  ],
  "guard_own_pid_records": [],
  "scope": "Two one-pass NCU captures, ordered copy then triad on 16MiB arrays with --cache-control none, separate from unprofiled timing. DRAM writes can differ from logical output bytes due to cache/writeback window; report discrepancy, not exact equality. L2 sector counts retained without treating them as algorithm bytes. No hardware ceiling or general memory workload peak claim.",
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